1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a metal contact in a semiconductor device using a metal contact pad.
2. Description of the Related Art
In order to increase the integration and cell capacitance of semiconductor devices, such as direct random access memories (DRAMs) where capacitors are formed on transistors, the height of the capacitors has been increased. An interlayer dielectric layer is etched to form contact holes which expose the surface of a lower layer to be contacted with a metal interconnection, thereby forming metal interconnection lines. However, as the interlayer dielectric layer becomes thick, it is unevenly etched. As a result, the surface of the lower layer may not be exposed.
Accordingly, to solve this problem, a technique for forming a metal contact using a metal contact pad is used. According to this technique, a conductive plug is formed. The conductive plug perforates a lower interlayer dielectric layer and short-circuits a lower layer, thereby forming a contact pad. An etch stopper is formed on the conductive plug. A contact hole which perforates an upper interlayer dielectric layer is formed to expose the etch stopper. The exposed etch stopper is etched to form a contact hole which exposes the conductive plug. In this technique, an etch stopper is formed to decrease the depth of an interlayer dielectric layer to be etched by the thickness of a metal contact pad. Thus, uneven etching is prevented and the surface of the lower layer is exposed.
However, in general, a plurality of metal contacts in a semiconductor device are simultaneously formed. For example, an active metal contact directly connected to an active region and a bit line metal contact directly connected to a bit line conductive layer are simultaneously formed. In this case, an upper interlayer dielectric layer is etched to form a contact hole which exposes an etch stopper and a bit line capping layer. The etch stopper in the active metal contact region and the bit line capping layer in the bit line contact region are simultaneously etched. However, in general, the bit line capping layer is thicker than the etch stopper. Thus, when the etch stopper has already been completely etched in the active metal contact region, the bit line capping layer is still being etched. As a result, a lower interlayer dielectric layer may be overetched, thereby short-circuiting a metal contact and a gate conductive layer. In this case, a semiconductor device may not perform properly.
To solve the above problems, it is an object of the present invention to provide a method of forming a metal contact in a semiconductor device by which misalignment and overetching can be better prevented.
According to the present invention, there is provided a method of forming a metal contact in a semiconductor device having an active metal contact region and a bit line contact region. In the method, gate stacks are formed on a semiconductor substrate. Gate spacers are formed on the sidewalls of the gate stacks. A lower interlayer dielectric layer is formed to cover the gate stacks and the gate spacers. First contact holes, which perforate the lower interlayer dielectric layer and expose an active region of the semiconductor substrate, are formed. The first contact holes are filled with a metal barrier layer and a conductive plug. An upper portion of the metal barrier layer is removed to form grooves around the upper sides of the conductive plug. The grooves are filled with an etch stopper. The lower interlayer dielectric layer is etched so that the etch stopper protrudes above the lower interlayer dielectric layer. A bit line stack is formed by sequentially stacking a bit line conductive layer and a bit line capping layer on the conductive plug in the bit line contact region. An etch stopper is formed on the conductive plug in the active metal contact region and bit line spacers at the sidewalls of the bit line stack in the bit line contact region. An upper interlayer dielectric layer is formed to cover the etch stopper, the bit line stack, and the bit line spacers. A portion of the upper interlayer dielectric layer is etched to form second contact holes which expose the etch stopper and the surface of the bit line capping layer. The etch stopper and the exposed portion of the bit line capping layer pattern are removed to form third contact holes which expose the conductive plug in the active metal contact region and the bit line conductive layer in the bit line contact region. The third contact holes are filled with a conductive layer.
In one embodiment, the gate stacks are formed by sequentially stacking gate dielectric layer patterns, gate conductive layer patterns, metal silicide layer patterns, and gate capping layer patterns.
In one embodiment, the lower interlayer dielectric layer has a thickness of 1500-1700 xc3x85 above the upper surface of the gate stacks.
In one embodiment, the grooves around the upper sides of the conductive plug have a depth of 500-700 xc3x85 and a width of 30-40 nm.
The etch stopper filling the grooves can be formed of a material having an excellent, i.e., high, etching selectivity to the lower interlayer dielectric layer. The lower interlayer dielectric layer may be a silicon oxide layer, and the etch stopper may be a silicon nitride layer.
To form the etch stopper and the bit line spacers, an etch stopper is formed on the lower interlayer dielectric layer to cover the etch stopper and the conductive plug in the active metal contact region and cover the etch stopper and the bit line stack in the bit line contact region. Next, a mask layer pattern is formed to cover the etch stopper in the active metal contact region. The etch stopper is etched by an anisotropic method using the mask layer pattern as an etching mask. The mask layer pattern is removed.
In one embodiment, the etch stopper in the active metal contact region protrudes above the lower interlayer dielectric layer.
The etch stopper can be formed of a material having an excellent, i.e., high, etching selectivity to the upper interlayer dielectric layer. The upper interlayer dielectric layer may be a silicon oxide layer, and the etch stopper may be a silicon nitride layer pattern.
The etch stopper can have a thickness of 300-600 xc3x85, and the bit line capping layer pattern can have a thickness of 1000-2000 xc3x85.
According to another embodiment of the present invention, there is a provided a method of forming metal contacts in a semiconductor device having an active metal contact region and a bit line contact region. In the method, gate stacks are formed on a semiconductor substrate. Gate spacers are formed on the sidewalls of the gate stacks. A lower interlayer dielectric layer is formed to cover the gate stacks and the gate spacers. First contact holes, which perforate the lower interlayer dielectric layer and expose an active region of the semiconductor substrate, are formed. The first contact holes are filled with a metal barrier layer and a conductive plug. An upper portion of the metal barrier layer is removed to expose the upper side of the conductive plug. The lower interlayer dielectric layer is etched so that the exposed upper portion of the conductive plug protrudes above the lower interlayer dielectric layer. A bit line stack is formed by sequentially stacking a bit line conductive layer pattern and a bit line capping layer pattern on the conductive plug in the bit line contact region. An etch stopper is formed on the conductive plug in the active metal contact region and bit line spacers are formed on the sidewalls of the bit line stack in the bit line contact region. An upper interlayer dielectric layer is formed to cover the etch stopper, the bit line stack, and the bit line spacers. A portion of the upper interlayer dielectric layer is etched to form second contact holes which expose the etch stopper and the bit line capping layer. The etch stopper and the exposed portion of the bit line capping layer pattern are removed to form third contact holes which expose the conductive plug in the active metal contact region and the bit line conductive layer in the bit line contact region. The third contact holes are filled with a conductive layer.
In one embodiment, to form the etch stopper and the bit line spacers, an etch stopper is formed on the lower interlayer dielectric layer to cover the conductive plug in the active metal contact region and the bit line stack in the bit line contact region. A mask layer pattern is formed to cover the etch stopper in the active metal contact region. The etch stopper is etched by an anisotropic method using the mask layer pattern as an etching mask. The mask layer pattern is removed.
The etch stopper in the active metal contact region can protrude above the lower interlayer dielectric layer.
The etch stopper can be formed of a material having an excellent, i.e., high, etching selectivity to the upper interlayer dielectric layer. The upper interlayer dielectric layer may be a silicon oxide layer, and the etch stopper may be a silicon nitride layer.
The etch stopper can have a thickness of 300-600 xc3x85, and the bit line capping layer pattern can have a thickness of 1000-2000 xc3x85.